Held on  July 20th…

SUBSTRATE NOISE COUPLING IN CMOS ICs

2:00-5:00 PM, July 20th  (Saturday)

….. Cost: Rs.1,500
Venue: Officespac.es, No.4164, 13th A Main, HAL 2nd stage, Indiranagar (on 8th cross, the road opp. 12th Main Coffee Day) …..
SPEAKER PROFILE - COMPLETED - VENUE MAP ….

We start with the topic of noise coupling in general, presenting the Aggressor-Victim view of noise coupling for various scenarios. Then we analyze the specifics of noise coupling through the Silicon substrate and identify strategies to counter the problem.

The analysis of the problem and solution for Substrate noise coupling takes us on an exciting journey across most facets of IC product development – package choices, design and layout techniques for noise reduction, IC fabrication and Silicon substrate choices, reliability considerations like ESD & Latchup, and board design careabouts. A physically intuitive picture emerges through analysis of current loops and by coming up with an electrical model for substrate isolation.

The speaker has authored 2 patents related to Substrate noise reduction and has delivered this seminar in 5 VLSI companies to more than 150 engineers.

WHO SHOULD ATTEND

Anyone who works on the IC design, layout, verification, characterization or board design of mixed signal ICs. Also relevant for anyone who wants to understand the full cycle of IC product development in the context of noise careabouts.

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TESTIMONIALS ….
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“Well presented and very well concluded…”

- Vikas Choudhary, Manager, Analog Devices

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“It was really a very effective seminar and the points that you focused on were very helpful from a design point of view”

- Jatinder Singh, Manager, Society for Integrated Circuit Technology and Applied Research (SITAR)

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“The session was very well conducted. The most important careabouts with respect to substrate noise were put together in a coherent fashion and would certainly help anyone designing mixed signal systems. Coming from someone who has faced and successfully solved some tough problems on the subject, the seminar had the depth and the rigor required to be immediately useful in real world designs. Your presentation style is clear and precise, making it even better. Highly recommended!””

- Ganesh Kiran, Chip lead, Texas Instruments

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‘Substrate Noise’ can become a nightmare for designers especially when it comes to mixed signal systems. Anand explained the sources of substrate noise, its impact on the performance and different strategies to resolve the same in a very systematic manner. Needless to mention that the clear insight into the subject is a result of his vast experience. And hence, most of these ideas are directly applicable to the practical designs. The flow of the seminar was very well maintained and addressed engineers from all the fields. A good one!

- Priyanka, Lead Engineer, Signalchip Innovations
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Feedback from the seminar

10- Outstanding! Practical approaches to Latch-up, ESD ring, Scribe ring well explained. - Prasad, LSI

By attending this session we came to know many things like domain separation, how ESD bus has impact on substrate noise, etc. We also understood what should be the solution adopted from different points of view like (a) which process to be used (b) techniques like deep NWELL (c) what kind of package to be used.  - Sandeep, Sankalp Semiconductors

10-Outstanding! The idea was introduced in good detail but not too much detail which would lead to confusion. The flow of the presentation was good. - Sahit, LSI

The big picture given about substrate noise coupling and factoring the problem gave a good understanding. - Chandra Patel, Broadcom

10-Outstanding! Gave an overview of noise at system level as well as device level. The flow of the seminar was very good, starting from different sources of noise to analyzing the problem. - Vinay, ST

10-Outstanding! Well-taught starting from basics, taking a deep dive into unknown areas and helping make trade-offs. - Purna, Intel