Here are some of the trainings we did. While we are no longer doing any trainings, we have left the information below intact as this is a useful list of topics for fresh grads to pick up.

MODULES-ON-DEMAND

 

oo  CMOS TECHNOLOGY oo

Introduction to CMOS devices

This module covers MOSFET device physics; terminal characteristics; first order and second order effects; operating regions; transistor modelling including parasitics; realization of various components like resistors, capacitors, switches etc. in a CMOS technology.

 
 

CMOS process technology

This module covers various fabrication steps involved in CMOS process; the construction of various components like MOSFETs, capacitors, resistors and inductors, the mapping of layers in Physical design to process steps and an introduction to DRC rules.

 
 

Introduction to Deep Submicron processes

MOSFET scaling challenges (leakage, DIBL), technology enablers for nodes like 28 nm (embedded SiGe, High K gate dielectric, metal gate, etc), minimum feature sizes in the TSMC 28 nm process. Effects of scaling on digital and analog circuits, modeling of deep Submicron transistors. FinFET vs. Coplanar proceses.

 
  IC PRODUCT OVERVIEW  
 

Introduction to the IC product flow

Overview of the ASIC flow & custom mixed-signal design and layout flows, tapeout and MEBES generation, mask manufacture, IC fabrication overview, IC packaging overview, IC test & characterization overview, IC qualification.

 
 

Introduction to the ASIC design flow

All design flow steps from RTL to GDS including RTL, Verification, Synthesis, PD, CTS, P&R, DFT – the goals and careabouts in each step, tools used in each step, Introduction to Scan/ATPG and BIST.

 
 

An IC designer’s guide to ESD and Latchup

Covers the topic of ESD and Latchup in a manner that is relevant to IC design and layout engineers. In addition to the theory behind these failure mechanisms and the way to counter them, the common IC design/ layout practices to counter them are also presented.

 
 

Introduction to IC packaging

Introduction to IC package construction, types of packages, electrical modelling of packages, common scenarios of performance degradation due to packages.

 
 

Introduction to thermal care-abouts in ICs

Theory behind thermal analysis, thermal characteristics of CMOS processes and packages, thermal modelling and common schemes used to improve thermal performances.

 
 

Introduction to IC reliability and qualification

Covers the topic of reliability of CMOS ICs. Terminologies related to reliability, mechanisms of failure, methods of quantifying reliability and enhancing it, the IC qualification procedure.

 
  SYSTEM/ APPLICATION  
 

Architecture of a wireless signal chain

The wireless signal chain is used to illustrate the various key components of any signal chain. Various blocks like Antenna, LNA, PLL, Mixer, PA, ADCs, DACs and filters are introduced and related to signal processing concepts. Interfaces and chip I/Os are also presented in context.

 
 

Introduction to Wireless specifications

Provides the theoretical background to understand the key specifications at the system level. RF specs like 1-dB compression point, IMD3, IIP3, Noise figure, Sensitivity and Dynamic range; Baseband specs including BER and EVM. 

 
 

Overview of Wireless technologies & terminologies

GPS, Bluetooth, WLAN, GSM-GPRS/EDGE, W-CDMA/UMTS, MBMS, LTE, HSPA, CDMA2000, TD-SCDMA, Zigbee

 
 

Introduction to Data converters

A quick introduction to the theory behind ADCs and DACs, ideal and non-ideal characteristics, Static and dynamic specifications, Sampling and Nyquist theorem, various architectures of ADCs (Flash, Pipelined, SAR, Sigma Delta) and their merits/ demerits, characterization of data converters.

 
 

Introduction to PLLs

Applications of the PLL, its block diagram, brief explanation of the constituent components, key specifications.

 
 

Introduction to I/Os

Key I/O specifications, CMOS I/Os, motivation for low voltage differential I/Os, LVDS & CML buffers, termination considerations.

 
 

Introduction to SERDES interfaces

High speed SERDES interfaces, key specifications, block diagram, PHY architecture and 8b10b coding, introduction to some important standards like USB and PCI Express

 
 

Introduction to serial communication protocols

Synchronous and asynchronous serial communication: UARTs, I2C, SPI interfaces

 
 

Introduction to IC power management

Need for power management, LDOs, Buck/boost converters, Bandgaps, PORs, Key specifications and considerations.

 
 

Overview of memories

Types of memories and applications – SRAM, ROM, Nand Flash, DRAM, etc – where each is used, merits and demerits

 
  TEST/ CHARACTERIZATION  
 

Overview of RF instruments

Theory of operation of RF instruments (Signal analyzers, Network Analyzers, VNA, Power meters). Theory of operation of DSO, DPO and sampling oscilloscopes

 
 

Testing concepts for data converter systems

Techniques to test each static and dynamic specification, understanding FFTs and using it as a debug tool

 
 

Testing concepts for high speed interfaces

Time interval error histograms, eye diagram, BER bathtub curves, deterministic vs. random jitter and debug techniques

 
 

Introduction to Signal integrity

Current loops and EMI/EMC, ground partitioning, signal current and return current analysis, decoupling capacitors (ideal vs. real), digital/ analog partitioning, optimum grounding strategy at the IC/ board/ system level.

 
 

Transmission lines, S-parameters and Smith charts

Transmission line theory: when and where to use, relevance and practical uses of S-parameter analysis, Smith charts and their usage, design of impedance matching networks

 
  DIGITAL DESIGN CONCEPTS  
 

Introduction to standard cells

This module covers MOS implementation of various digital blocks such as inverters, gates, multiplexers, flops etc; their performance parameters such as rise time, fall time, setup time and hold time are related to various MOS parameters; how to optimize these performance parameters, layout of standard  cells.

 
 

Digital Design Concepts

Combination and sequential circuits; optimization techniques like K-map; Finite state machines; Synchronous and asynchronous counters; Timing analysis; Pipelining; Optimization methods.

 
 

Digital design using HDL (VHDL or Verilog)

How HDL is different from C; HDL syntax and their care-abouts; illustration using various design examples. Levels of abstraction, Truth tables & K-maps, Gates, Combinational & sequential circuits, VHDL constructs & syntax, implementation styles (behavioural, data flow, structural), Data types, Finite state machines, Arithmetic operations, Inertial, transport and delta delay concepts

 
 

Timing careabouts for Digital designs

Synchronous & asynchronous design, Delay, setup/ hold, skew, slack, clock jitter, handling multiple clock domains, introduction to Static timing analysis and concept of timing arcs

 
 

Low power trends in Digital design

Gate leakage and challenges in digital power consumption in 28 nm/ 20 nm technologies, Power gating, Clock gating, power collapse, low leakage/high Vt transistors, implementation of foot switch/ head switch, voltage scaling (AVS, DCVS, SVS), low power techniques in standard cell and memory design

 
  ANALOG DESIGN/LAYOUT CONCEPTS  
 

Basic Analog Concepts

Domains of circuit analysis like Time, Frequency & s-domain.; visualizing frequency response from the pole/zero locations in the s-domain; types of analysis in SPICE like OP, DC, AC, Tran, Noise, Distortion; amplifier topologies, their small-signal and large signal behaviour, gain, input-output impedances, and trade-offs 

 
 

Advanced Analog concepts I

Need for feedback and its advantages; Stability problems with the feedback circuits, Theoretical foundation of phase margin and how it relates to the frequency and transient response of a feedback system; Analysis of two pole amplifiers in feedback; Compensation techniques for a two-pole amplifier.

 
 

Advanced Analog concepts II

Sources of Noise and distortion in analog circuits and analysis; designing for specifications like PSRR, CMRR, SNR, and SINAD; Common-mode feedback circuits, Switched capacitor circuits.

 
 

Custom Analog Layout Design

This module covers familiarization of layers & relationships to components; Layout of basic devices: NMOS, PMOS, Resistor, Capacitor; Drain-sharing techniques; DRC rules and how are they related to fabrication tolerances; DRC/LVS verification; Digital standard cell layouts; Optimization for minimum parasitics and area; Various types of resistor and capacitors;  Analog layout concepts: matching, common centroid, half-cell; differential amplifier layout; Routing, Coupling & Shielding; ESD & Latchup considerations; Electro-migration effects and metal width calculations 

 
  ANALOG IP DESIGN  
 

Bandgap reference Design

Basic principle of Bandgap design; understanding various specifications (supply range, reference voltage, accuracy, PSRR, noise, start up time); sources of noise and inaccuracy; stability; start up issues; How to simulate various performance parameters; How to design for a given specification illustrated through a design example.

 
 

Regulator Design

Block diagram; various components (reference, pass element, sampling resistor and error amplifier); understanding specifications(input range, IQ, accuracy, line and load regulation, drop-out voltage, start up time, PSRR, noise); sources of performance degradation; Design example.

 
 

I/O buffer design

This module covers various aspects of input-output buffer design; High speed IO buffers design constraints and topologies; CMOS buffers; LVDS buffers; CML buffers, How to avoid EMI issues; Matching consideration to avoid reflections; signal integrity issues; Designing to a standard.

 
 

ADC design

Overview of the design of Flash, Pipeline, SAR and Sigma delta ADCs. Mapping the specifications to the block designs

 
 

High speed DAC design

DAC architectures and design care-aboutsfor a high speed current steering DAC

 
 

Design of filters

Filter specifications and types (Chebychev, Butterworth, etc), design of active filters, biquads, etc.

 
  RF BLOCK DESIGN  
 

Design of RF LNAs

LNA architectures, impedance matching concepts, noise analysis

 
 

Design of RF VCOs and PLLs

RF VCO architectures, phase noise analysis, RF PLL loop synthesis and analysis

 
 

Design of RF mixers

Downconversion and upconversion mixer topologies and design

 
 

RF Power amplifiers

Power amplifier topologies, analysis of non-linearity and efficiency, PA linearization schemes

 
   

SOME CUSTOMIZED COURSES/ SEMINARS

   

WIRELESS SYSTEM COURSE

36 hours
The Wireless systems course aims to uncover the workings of the Wireless signal chain from Digital baseband to the antenna. The mechanism of voice/data getting modulated, pulse-shaped, up-converted and amplified is taught in a step-by-step manner. System-level specifications are discussed for the 802.11a/b/n standards and are mapped to the specifications of the individual blocks in the analog/RF sections of the transmit and receive signal chains. Overview of each block design is also provided and the effect of block impairments on the system level performance are discussed. Advanced concepts like PA linearization, PLL Injection locking and impedance matching at the antenna-LNA interface are covered in depth. This course can be tailored to a different wireless standard on request. =
TESTIMONIALS ….

“The course covers the system-level aspects for RFIC circuit engineers. The course will surely enable better view  for algorithm development for communication system and brings insight into the performance/impairments of the radio system in a communications chip.  The course was interactive and course materials are a good  reference.”

-  Guru Revanna, Manager, WLAN team, Broadcom

Anand has a very good understanding of the circuit level realization of the wireless signal chain. He also has a good grasp of various RF impairments and can relate them to various circuit theory concepts in a easily understandable way.” 

- Manohar, Scientist, Sr.Staff, Broadcom

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RF TEST & CHARACTERIZATION

 36 hours
This course deals with the test and characterization concepts for Wireless systems. It covers the system-level specifications like Sensitivity, EVM, BER as well as the testing methodology for the 802.11a/b/n standards. Also covered in-depth are concepts like Smith charts and their applications, S-parameters, FFT basics, Phase noise, etc. The analysis of unintentional antennas, EMI, EMC in RF systems and ways to solve EMI issues are explained. High speed I/O standards like PCI Express, USB 3.0 as well as serial communication standards like UART, SPI are covered. The operating principles of test equipment like Spectrum & Network Analysers, Oscilloscopes like DSO and DPO are explained. -
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BANDGAP DESIGN SEMINAR

 IN PARTNERSHIP WITH MENTOR GRAPHICS
This seminar presents a step-by-step approach to design a Bandgap reference circuit using the Mentor Graphics Pyxis/ Eldo platform. Starting with basic concepts of positive and negative temperature coefficients, the design methodology for the Bandgap reference circuit is developed in a step-by-step manner. The complete simulation methodology including DC temperature sweep, AC analysis for loop stability, noise simulations and transient simulations for evaluating the Startup circuit is presented. =
TESTIMONIALS ….

 The Bandgap seminar was good. I enjoyed attending it. I learnt a better understanding not only about the bandgap working but also about the eldo tool’s functionality eg. Lstb and Alter.

Keep it up. Hoping to see more advanced seminars to see how Eldo can help design high precision analog stuff.” 

-  Sanjeev (Cypress Semiconductor)

The bandgap reference seminar conducted by Mentor and Sahyogee exceeded our expectations. The technical aspects of the bandgap reference block discussed was very detailed and we were surprised that it was covered in such a short duration with a lot of clarity. The features of eldo which were discussed were also very relevant and will help us in designing almost any block in an efficient manner. We are happy that we have such a strong tool in our hands. Looking forward to more such workshops….” 

- Nikhil (Signalchip Innovations)

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SUBSTRATE NOISE COUPLING IN CMOS ICs

SPEAKER PROFILE - COMPLETED - VENUE MAP ….

We start with the topic of noise coupling in general, presenting the Aggressor-Victim view of noise coupling for various scenarios. Then we analyze the specifics of noise coupling through the Silicon substrate and identify strategies to counter the problem.

The analysis of the problem and solution for Substrate noise coupling takes us on an exciting journey across most facets of IC product development – package choices, design and layout techniques for noise reduction, IC fabrication and Silicon substrate choices, reliability considerations like ESD & Latchup, and board design careabouts. A physically intuitive picture emerges through analysis of current loops and by coming up with an electrical model for substrate isolation.

The speaker has authored 2 patents related to Substrate noise reduction and has delivered this seminar in 5 VLSI companies to more than 150 engineers.

WHO SHOULD ATTEND

Anyone who works on the IC design, layout, verification, characterization or board design of mixed signal ICs. Also relevant for anyone who wants to understand the full cycle of IC product development in the context of noise careabouts.

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TESTIMONIALS ….
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“Well presented and very well concluded…”

- Vikas Choudhary, Manager, Analog Devices

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“It was really a very effective seminar and the points that you focused on were very helpful from a design point of view”

- Jatinder Singh, Manager, Society for Integrated Circuit Technology and Applied Research (SITAR)

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“The session was very well conducted. The most important careabouts with respect to substrate noise were put together in a coherent fashion and would certainly help anyone designing mixed signal systems. Coming from someone who has faced and successfully solved some tough problems on the subject, the seminar had the depth and the rigor required to be immediately useful in real world designs. Your presentation style is clear and precise, making it even better. Highly recommended!””

- Ganesh Kiran, Chip lead, Texas Instruments

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‘Substrate Noise’ can become a nightmare for designers especially when it comes to mixed signal systems. Anand explained the sources of substrate noise, its impact on the performance and different strategies to resolve the same in a very systematic manner. Needless to mention that the clear insight into the subject is a result of his vast experience. And hence, most of these ideas are directly applicable to the practical designs. The flow of the seminar was very well maintained and addressed engineers from all the fields. A good one!

- Priyanka, Lead Engineer, Signalchip Innovations
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Feedback from the seminar

10- Outstanding! Practical approaches to Latch-up, ESD ring, Scribe ring well explained. - Prasad, LSI

By attending this session we came to know many things like domain separation, how ESD bus has impact on substrate noise, etc. We also understood what should be the solution adopted from different points of view like (a) which process to be used (b) techniques like deep NWELL (c) what kind of package to be used.  - Sandeep, Sankalp Semiconductors

10-Outstanding! The idea was introduced in good detail but not too much detail which would lead to confusion. The flow of the presentation was good. - Sahit, LSI

The big picture given about substrate noise coupling and factoring the problem gave a good understanding. - Chandra Patel, Broadcom

10-Outstanding! Gave an overview of noise at system level as well as device level. The flow of the seminar was very good, starting from different sources of noise to analyzing the problem. - Vinay, ST

10-Outstanding! Well-taught starting from basics, taking a deep dive into unknown areas and helping make trade-offs. - Purna, Intel

 

   

INTRODUCTION TO ADCs

 

 

   
SPEAKER PROFILE - COMPLETED - VENUE MAP

 

With a strong emphasis on signal processing in the digital domain, today’s electronics relies heavily on ADCs – the “eyes” of the signal chain to the real world.  We present a simplistic and highly intuitive derivation of different ADC architectures – FLASH, SAR, PIPELINE & SIGMA-DELTA. Each type of ADC has its unique architecture which gives it unique merits and demerits. We present each architecture as a unique solution to the following problem statement: “If I have an unknown weight and I need to estimate its weight to the resolution of 1 kg, what are the different ways I can come up with the estimate?” Each method of solving this problem gives rise to an ADC architecture!

Relying only on logic, and without cumbersome mathematical equations to worry about, a very intuitive understanding of ADCs emerges. Looked at from this intuitive manner, the merits and demerits of each architecture become immediately obvious. The application of where a given ADC architecture gets used also become very evident. The state-of-the-art ADC of each type is also briefly presented.

The speaker has led several SoC designs involving high-end ADCs and has delivered this seminar in 3 VLSI companies to more than 100 engineers.

=
 
   
WHO SHOULD ATTEND

Anyone who wants to understand the basic principles of analog to digital data conversion. Mixed signal design, test and characterization engineers, system designers and application engineers will find this a great introduction to ADC architectures, applications and tradeoffs.

 
   
TESTIMONIALS ….
 

“Excellent intuitive way to understand ADCs. I wish colleges teach subjects in this manner. I am sure engineers in every Semiconductor industry will benefit from this presentation.” 

-  Ramanujam (Director of Analog/RF, MaxLinear)

 
 

“Very intuitive explanations of basic concepts with the right analogies. Very much satisfying indeed.” 

- Pradeep, Broadcom

 
 

“Excellent analogies and one of the best ways to understand ADC architectures.” 

- Phaneendra, Tessolve

 
 

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Feedback from the seminar 

Concepts of Sigma Delta ADC was very good and is a novel way to explain.

- Soman, TI

Presentation of different architectures with examples was really good.

- Ram, LSI

Excellent explanation of ADCs (especially Pipelined and Sigma delta). 

- Sahit, LSI

 

FOUNDATIONS OF WIRELESS & CELLULAR

 
 

 

….. ….. Cost: Rs.1,500 
–    ….
. .  

 

Cellular technologies have evolved from the days of Analog-based 1G to the now popular 3G. At the same time, Wireless technologies have evolved from the 1 Mbps 802.11 standard to the 1+ Gbps 802.11ac standard. This seminar presents an overview of the journey of “communication without wires” over a good part of the last century. It includes an explanation of the working principle behind competing cellular standards like CDMA and GSM, technology enablers like OFDM and MIMO, as well as the convergence of Wireless and Cellular technologies in 4G.

A generic signal chain of a wireless system is presented and the function of each block in Digital baseband, Analog and RF sections explained. Key principles of digital modulation including complex I-Q modulation and Shannon’s theorem are succintly explained. A sample link budget is shown to create an appreciation of various challenges involved in the design of these systems. 

 
 
WHO SHOULD ATTEND

Engineers working on ICs or systems for wireless or cellular technologies will find this seminar an eye-opening look at the “big” picture. This includes those working on the digital design, analog/RF design, algorithms, software and system/ hardware aspects of these technologies. It is also a very useful re-look at concepts in a very different manner for students of engineering. A very basic Communications background is assumed.

 
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TESTIMONIALS
It covered 3 subjects of my B.Tech! For the first time, I started appreciating Information theory, Shannon’s theorems, concept of complex mixing, etc. Analogies were great.- Ratna Kumar, Characterization engineer, Texas Instruments
 aaa  
Presentation was excellent. Analysis was quite thorough.- Rahul, Analog designer, Texas Instruments  
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10/10 – Outstanding. Can’t get better!- Sourabh, System & Application engineer, Texas Instruments
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